Airgaps are currently employed in semiconductor devices, such as integrated circuit (IC) devices as both structural or functional (e.g., circuit) element. Also, airgaps in the form of cavities may be present in MEMS and NEMS devices. The use of airgaps is considered to be very promising in the technology area of circuit interconnects, where airgaps may be used as a dielectric for isolation of such interconnects. As the geometries of IC technologies scale down, interconnects are becoming one of the major limiting factors of improved signal propagation delay times, reduced dynamic power consumption and reduction of signal errors resulting from cross-talk effects between adjacent metal lines. Some improvement has been realized by the semiconductor industry's transition from the use of aluminum to the use copper as an interconnect material. This has change has resulted in a reduction in the resistance of IC interconnects, and thus improvements in propagation delays and reductions in dynamic power consumption.
A current focus in the semiconductor industry is to achieve better isolation between the interconnect lines through the introduction of materials with lower dielectric constant than that of silicon oxide (k=4.2) in order to reduce the capacitance (C) between lines. However, the integration of low-k materials (k<3.0) into IC production processes creates a number of challenges associated with leakage, mechanical instability and joule heating, increasing the overall cost of future IC processes. Additionally, the barrier and intermediate layers that employed in such processes tend to increase the effective permittivity of the final stack, which is undesirable from a circuit performance standpoint.
The dielectric and electrical insulation properties of air makes the integration of airgaps as isolation between metal interconnect lines in IC device desirable in order to address some of the concerns discussed above. In fact, the approach of using of air as a dielectric to isolate electrical interconnects has been employed to reduce resistive-capacitive (RC) delay, as well as to reduce dynamic power consumption and signal errors (e.g. due to cross-talk between adjacent metal lines).
One approach that has been used to introduce air cavities into IC devices involves isotropic etching of a device. Such a process has been employed in the production of MEMS devices. This approach includes using hydrofluoric acid (HF) to dissolve a sacrificial SiO2 layer. In such a technique, a film that is relatively non-reactive with HF (e.g., SiC) is employed as an etch stop. The etch source is then sealed by a non-conformal CVD SiO2 layer.
Another approach for the introduction of air cavities is the use anisotropic etching. This approach includes eliminating material using an anisotropic dry etch. A mask is then used as part of the dry etch and strip operations. Subsequently, a conformal CVD SiO2 film, followed by a non-conformal CVD SiO2 film, is deposited on top of the lines to be used for the creation of airgaps.
U.S. Pat. No. 6,268,261 describes a process for manufacturing a semiconductor circuit that includes the use of airgaps. This process includes creating a plurality of adjacent conductive lines with a solid fill material between the conductive lines. One or more layers are formed above the lines and the fill material and one or more pathways to the fill material are formed through the layers formed above the lines and the fill material. The fill material is then converted to a gas that escapes through the pathways. This process leaves air voids between adjacent lines. The process results in a multi-layer semiconductor circuit with conductive lines, where the lines have airgaps (or voids) as a dielectric between them. This process has certain drawbacks, however. For example, the solid fill material needs to be deposited between the conductive lines. This fill material must be stable during deposition of the layers on top and be of a composition that is easily convertible to a gas. Further, in designing such circuits, the layers on top of a pathway need to be accounted for. Therefore, such an approach involves research and development of fill material compositions, circuit design considerations, and additional manufacturing operations, such as extra masking and etching steps.